Semiconductor dice include patterns of bond pads in electrical communication with integrated circuits contained on the dice. Bumped semiconductor dice include solder bumps formed on the bond pads. The solder bumps allow the dice to be flip chip mounted to substrates, such as printed circuit boards, to form multi chip modules and other electronic assemblies. Other semiconductor components, such as chip scale packages, can also include solder bumps which allow electrical connections to be made to the packages.
Different fabrication processes have been developed by semiconductor manufacturers for forming solder bumps. A typical wafer-level fabrication process utilizes solder wettable pads deposited on aluminum bond pads. The wafer can include a passivation layer, such as BPSG glass, having openings on which the solder wettable pads are formed. Typically, the pads include an adherence layer, such as chromium, which provides adherence to the bond pads and passivation layer. The adherence layer also forms a barrier to prevent the solder bumps from reacting with the bond pads. In addition to the adherence layer, the pads can include a solder wettable layer, such as copper, or other metal having a solderable metallurgy.
Typically, the pads are formed by evaporating, chemical vapor depositing, or electrodepositing the different metal layers through the openings in the passivation layer and onto the bond pads. Following deposition, the solder bumps can be reflowed at about 350.degree. F. to melt and homogenize the bumps. The reflow process also forms the bumps into a hemispherical shape.
Metal masks, or stencils, are typically utilized for depositing the adherence and solder wettable layers onto the bond pads, and for depositing the solder bumps onto the solder wettable pads. Sometimes different masks are employed for each deposition step. For a wafer level bump fabrication process, the masks must be aligned and secured to the wafer each time using tooling fixtures. In general, aligning and securing the masks to the wafers is a time consuming and labor intensive process.
In addition, the wafer is often subjected to high temperatures during the bump fabrication process and during reflow of the solder bumps. With semiconductor components it is desirable to maintain a low thermal budget during manufacture, to prevent degradation of semiconductor devices contained on the component. Accordingly, low temperature bump fabrication processes would be advantageous in fabricating bumped semiconductor components.
Still further, vacuum deposition processes, such as evaporation, CVD and electrodeposition, require fabrication equipment used by manufacturers for other semiconductor fabrication processes. However, some metals utilized in fabricating solder bumps, particularly copper, can be contaminants to other fabrication processes. Accordingly, it would be advantageous to perform the bump fabrication process without subjecting other semiconductor fabrication processes to contaminants.
Yet another shortcoming of electronic assemblies that include conventional bumped semiconductor components is that the metals used to fabricate bumps are relatively incompressible. The bumps are thus subject to cracking due to handling and thermal stresses placed on the components and substrates.
Resilient materials such as conductive elastomers can also be used to make electrical connections between semiconductor components and mating components. The resilient materials are able to absorb stresses better than conventional solder bumps. However, conductive elastomeric bumps require relatively complicated deposition and curing processes. One procedure that must be followed to insure low resistance electrical paths through the bumps is curing the bumps under compression. Curing the bumps under compression requires the use of weights or fixtures for biasing the components together.
It would be advantageous to fabricate bumps with resilient materials, such as conductive elastomers, but with simplified deposition and curing processes. Accordingly improved methods for fabricating bumped semiconductor components, and for fabricating assemblies that include bumped components would be welcomed in the art.